;80188 control
;By Zhu Shunyu

         UMCR    EQU    0FFA0H ; Upper Memory Control Register
         LMCR    EQU    0FFA2H ; Lower Memory control Register         
         PCSBA   EQU    0FFA4H ; Peripheral Chip Select Base Address
         MPCS    EQU    0FFA8H ; MMCS and PCS Alter Control Register
		 MMCS 	 EQU    0FFA6H ; Mid-Range Memory Control Register


; Initial 80C188XL UCS Pin
; |start address|block size| value for No waits, No Ready   
;   FE000H            8K                 3E04H
;   FC000H           16K                 3C04H
;   F8000H           32K                 3804H
 
         
; Initialize Upper Chip Select pin with 8K ROM 
;         MOV DX, UMCR
;         MOV AX, 03E04H
;         OUT DX, AX

; Initialize Lower Chip Select pin with 8k RAM
;         MOV DX, LMCR
;         MOV AX, 01C4H  ; Starting address 1FFFH, 8K, No waits, last shoud be 5H for 1 waits      
;         OUT DX, AL


; Timer control Unit
  
         T2_CON    EQU      0FF66H ; Timer 2 Control Register
         T2_CA     EQU      0FF62H ; Timer 2 compare register
         T2_CNT    EQU      0FF60H ;

         T1_CON    EQU      0FF5EH ;
         T1_CB     EQU      0FF5CH ;
         T1_CA     EQU      0FF5AH ;
         T1_CNT    EQU      0FF58H
         
         T0_CON    EQU      0FF56H ;
         T0_CB     EQU      0FF54H ;
         T0_CA     EQU      0FF52H ;
         TO_CNT    EQU      0FF50H   
         
; Timer Control Data


;Interrupt Control Registers
      

	INT3_CTRL	EQU 0FF3EH ;Interrupt 3 Control Register
	INT2_CTRL	EQU 0FF3CH
	INT1_CTRL	EQU 0FF3AH
	INT0_CTRL	EQU 0FF38H
	TIMER_CTRL	EQU 0FF32H ;Timer Interrupt Control Register
	ISR		EQU 0FF30H ; Interrupt Status Register
        EOI             EQU 0FF22H ; END OF INTERRUPT REGISTER
	
        IMKW            EQU 0FF28H ; Interrupt Mask 
        IPMK            EQU 0FF2Ah ; Interrupt Priority Mask 

;| - | - | - | - |MSK|PM2|PM1|PM0| For TCU INT

;| - |SFNM|CAS|LVL|MSK|PM2|PM1|PM0| For TCU INT0,1

;MSK 1-enable, 0-mask int 
;pm0-pm1 Priority

    
